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A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

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14 Author(s)
Hongil Yoon ; Memory Product & Technol. Div., Samung Electron. Co. Ltd., Kyungki, South Korea ; Gi-Won Cha ; Changsik Yoo ; Nam-Jong Kim
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A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-μm CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 11 )

Date of Publication:

Nov 1999

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