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A 500-MHz pipelined burst SRAM with improved SER immunity

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15 Author(s)
H. Sato ; Mitsubishi Electr. Corp., Hyogo, Japan ; T. Wada ; S. Ohbayashi ; K. Kozaru
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This paper describes a 0.25-μm, 64 K×36 bit pipelined burst SRAM using a 6.156-μm2 cell. It realizes over 500-MHz operation using a lower cost double metal process, Internal 16 K×144 organization by T-shaped bit line array reduces 20% of latency, 20% of active power, and 8.5% of die size. The low power also enables us to use lower cost thin quad flat type packages. Our solution to the soft error problem, a shallow triple well structure and four-transistor cell with stacked capacitor, improved soft error rate by 3.5 orders of magnitude compared with the conventional SRAM cell

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 11 )