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An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

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8 Author(s)
Mizuno, H. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Ishibashi, K. ; Shimura, T. ; Hattori, T.
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A low-standby-current 1.8-V, 200-MHz microprocessor has been fabricated with a 0.2-μm, five-metal, dual-oxide-thickness, CMOS technology and two power down modes (i.e., a standby mode and a data-retention mode). The microprocessor uses a switched substrate-impedance scheme to bias substrates in the standby mode while maintaining a 200-MHz operating speed. Data-retention capability during the standby mode is also maintained. This mode achieves 46.5-μA standby current. The microprocessor also offers a battery-backup capability in a self-substrate-biased data-retention mode. This makes it possible to apply a deep substrate bias without increasing the gate-induced drain leakage current or p-n junction current. The current consumption is only 17.8 μA when operating off a 1-V supply in the data-retention mode

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 11 )