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Scheduling a reservation primitive for effective latency hiding in DSM

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4 Author(s)
Hirota, M. ; Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan ; Yamazaki, T. ; Yonezawa, N. ; Wada, K.

Distributed shared memory (DSM) systems potentially have both performance scalability and good programmability. However, they also have a drawback in their difficulty in overlapping computation with inter-processor communication. For DSM systems, we propose a novel coherence protocol called Selective Validity Control (SVC) protocol. In the SVC protocol, a new memory access operation called a link access is introduced to hide the read miss latency and to rearrange allocation for shared data. However, in order to have a link access work effectively, it has to be scheduled appropriately. The paper proposes a scheduler that collects and analyzes memory accesses of an application program, and automatically schedules link accesses. The effectiveness of the link access is also described. To evaluate the performance of the scheduler, a trace-driven simulator for a DSM system has been developed. Bitonic sort and FFT programs from the SPLASH-2 benchmark suite are executed on the simulator. The results of the evaluation show that the read miss penalty and overall execution time can be reduced by using link access operations scheduled by our proposed scheduler

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Communications, Computers and Signal Processing, 1999 IEEE Pacific Rim Conference on

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