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Low power synthesis of dual threshold voltage CMOS VLSI circuits

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2 Author(s)
Sundararajan, V. ; Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA ; Parhi, K.K.

The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1 V and threshold voltage as low as 0.2 V the subthreshold leakage power of transistors starts dominating the dynamic power. Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consumption. We present a near-optimal approach to synthesize low static power CMOS VLSI circuits with two threshold voltages that reduces power consumption compared with a previous approach by up to 29.45%. Also, presented is a technique which finds static power optimal configurations for CMOS VLSI circuits when an arbitrary number of threshold voltages are allowed.

Published in:

Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on

Date of Conference:

17-17 Aug. 1999