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In this paper we present an approach to calculate lower and upper bounds for the switching activity in scheduled data flow graphs. The technique can be used to prune the design space in high level synthesis for low power before allocation and binding of functional units and registers. The low power allocation and binding problem is formulated. It is shown that this problem can be relaxed to the bipartite weighted matching problem which is solvable in O(n/sup 3/) where n is the number of functional units or registers, respectively. The application of the technique on benchmarks shows the tightness of the bounds. Most of the investigated bounds were less than 1% off the minimum respectively maximum solutions.