By Topic

Power minimization of high-performance submicron CMOS circuits using a dual-V/sub dd/ dual-V/sub th/ (DVDV) approach

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
M. M. Khellah ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; M. I. Elmasry

A new method, called DVDV, for low-power design of high-performance CMOS logic circuits is presented. DVDV utilizes a library of gates with dual supply voltages (V/sub dd/) and dual threshold voltages (V/sub th/) to achieve high-performance with minimum dynamic and leakage power. A Depth-First-Search (DFS) based heuristic for DVDV node assignment is described. Exercising the techniques on a set of benchmarks shows significant power savings over the dual-V, (with a single V/sub th/) scheme, and faster speeds than those possible with the dual-V/sub th/ (and a single V/sub dd/) approach.

Published in:

Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on

Date of Conference:

17-17 Aug. 1999