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A new method, called DVDV, for low-power design of high-performance CMOS logic circuits is presented. DVDV utilizes a library of gates with dual supply voltages (V/sub dd/) and dual threshold voltages (V/sub th/) to achieve high-performance with minimum dynamic and leakage power. A Depth-First-Search (DFS) based heuristic for DVDV node assignment is described. Exercising the techniques on a set of benchmarks shows significant power savings over the dual-V, (with a single V/sub th/) scheme, and faster speeds than those possible with the dual-V/sub th/ (and a single V/sub dd/) approach.