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Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end (the focus of this paper), and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in the subthreshold region. We analyze both CMOS and Pseudo-NMOS logic families operating in the subthreshold region. We compare the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Our results show an energy per switching reduction of two orders of magnitude for an 8/spl times/8 carry save array multiplier when it is operated in the subthreshold region.