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Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/

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5 Author(s)
Chin, A. ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Liao, C.C. ; Lu, C.H. ; Chen, W.J.
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We report a very simple process to fabricate Al/sub 2/O/sub 3/ gate dielectric for CMOS technology with k (9.0 to 9.8) greater than Si/sub 3/N/sub 4/. Al/sub 2/O/sub 3/ is formed by direct oxidation from thermally evaporated Al. The 48 /spl Aring/ Al/sub 2/O/sub 3/ has /spl sim/7 orders lower leakage current than equivalent 21 /spl Aring/ SiO/sub 2/. A good Al/sub 2/O/sub 3/-Si interface was evidenced by the low interface density of 1/spl times/10/sup 11/ eVcm/sup -2/ and compatible electron mobility with thermal SiO/sub 2/. Good reliability is measured from the small stress induced leakage current (SILC) after 2.5 V stress for 10,000 s.

Published in:

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

14-16 June 1999

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