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A self-aligned stacked capacitor using novel Pt electroplating method for 1 Gbit DRAMs and beyond

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10 Author(s)
Horii, H. ; Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin, South Korea ; Byoung Taek Lee ; Han Jin Lim ; Suk Ho Joo
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We first developed a novel self-aligned electroplating process to fabricate Pt electrodes for integrated high-dielectric capacitors. Electroplated Pt filled 120 nm-wide buried contact (BC) holes (aspect ratio 2:1). Pt pillars of 210 nm diameter and 650 nm height were successfully fabricated. The leakage current density of sputtered BST capacitors using electroplated bottom Pt was less than 200 nA/cm/sup 2/ at /spl plusmn/1.5 V. The oxide-equivalent thickness T/sub oxeq/ and dissipation factor of 40 nm-thick BST films were 0.70 nm and 0.0080 at 0 V, respectively.

Published in:

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

14-16 June 1999