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High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme

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3 Author(s)
Tsuji, K. ; Silicon Syst. Res. Labs., NEC, Sagamihara, Japan ; Takeuchi, K. ; Mogami, T.

It is demonstrated that low temperature activation of the source/drain impurities, induced by the re-crystallization of an amorphous substrate layer, is effective for realization of scaled CMOS with abrupt junction profiles. Physical 50 nm gate length pFETs with high drive current and good short channel behaviour were obtained.

Published in:

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

14-16 June 1999