Minimizing the cost of low K dielectric manufacturing implementation

The integration of organic low k interconnection dielectric materials into wafer fab manufacturing processes requires changes to the equipment set and the process sequence. The capital investment required for conversion and the impact of the new equipment and materials on the finished wafer cost are a concern to wafer manufacturers. We have modeled the costs of converting 180 nm logic/microprocessor fabs from Al/W/SiO/sub 2/ and Cu/SiO/sub 2/ dual damascene interconnect processes to Al/W/Low-k and Cu/Low-k processes. Equipment was chosen to minimize the capital outlay required for conversion. The output of the models includes equipment capital requirements: changes to staffing and facilities costs, and the cost of finished wafers. Our results indicate that conversion to low k processing should require only modest capital expenditures and effects the finished wafer costs by less that 5%. For example, one case study shows 10% of a fab's capacity could be converted from Al/W/SiO/sub 2/ interconnect technology to Al/W/Low-k by the addition of a wafer apply track. In this case wafers with the Al/W/Low-k interconnection technology are produced in a new fab at a lower cost than those with Al/W/SiO/sub 2/ interconnection technology.