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Minimizing in-line calculated yield errors by optimizing and maintaining ADC classifier performance

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5 Author(s)
Blais, J. ; IBM Microelectron., Essex Junction, VT, USA ; Pilon, T. ; Robitaille, C. ; Bartholomew, K.
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Automatic defect classification (ADC) has become a standard tool to monitor and manage yield-limiting defects in the semiconductor industry. The ADC system is more productive than manual classification systems because of its greater accuracy, consistency, and throughput. Engineers have used it to assist in yield learning, monitoring for excursions, and making in-line yield predictions. Semiconductor manufactures use in-line yield predictions to adjust wafer starts and appropriately disposition lots. This paper explores the quality of the in-line defect-limited yield (DLY) prediction as a function of ADC system performance. When the ADC system is operating optimally, the in-line DLY error is minimized. Maintaining optimal system performance is a two-part project. First, system hardware must be appropriately calibrated and maintained. Secondly, the ADC classifier set-ups must be optimized. ADC classifier performance is measured with two values: accuracy and purity. The relationship between accuracy, purity, and error in the PLY calculation is described. Techniques to optimize classifier performance are discussed. Programmed defect standard wafers (PDSW) are a proven means to monitor the health of inspection tools. A particular PDSW, known as TDS, provides benefits over conventional PDSWs in that it may be used on a variety of inspection tools and is a challenging and sensitive measure of ADC performance. The improvement of in-line defect-limited yield caused by the implementation of the TDS is explored. The impact of in-line DLY prediction on overall fabricator productivity is also discussed

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

Date of Conference:

1999