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Analysis and reduction of defects induced by in-line wafer probing

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3 Author(s)
Polavarapu, M. ; Semicond. Technol. Center, Lockheed Martin Fed. Syst., Manassas, VA, USA ; Peters, J. ; Wright, S.

Parametric and defect testing of drop-in or scribe line test structures after first level metal patterning is highly desirable since it offers rapid feedback for device or defect related issues in the front end of the line (FEOL). This assumes even more significance considering the dramatic increase in the levels of metallization made available by the chemical-mechanical polishing (CMP) technology and the corresponding increase in cycle time in the Back End Of the Line (BEOL). However, the potential for introduction of defects from such a seemingly innocuous operation as in-line test is frequently overlooked. This paper describes the significance of such defects, a method of monitoring the defect levels and the steps taken to reduce them

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Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

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