By Topic

A methodology for determining capacity consumption due to the sampling of lots within the photolithography metrology sector in a multi-part number, multi-technology fabricator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Butler, K.L. ; IBM Microelectron., Essex Junction, VT, USA ; Woods, R.

The current semiconductor business environment requires companies to provide their customers with many chip design options. This drives a large diversification in product and technology mix within a given fabricator, and as the cost of measurement tools, fabricator space, and manpower increases, it becomes critical that each tool is utilized effectively for the situation. An effective way to optimize the utilization and capacity of the photolithography metrology toolset is to implement a plan that allows it to measure less than 100% of the wafers scheduled to move through the area. Metrology capacity utilization is primarily determined by the execution of a sample and skip plan that allows the fabricator to measure less than every wafer and less than every lot. Traditionally, these plans are determined by the technology ground rules of the product and the technology specifications of the photolithography toolset. More stable processes, such as those in older technologies, are allowed higher sampling and skipping rates. The planning process, however, typically does not have a feedback mechanism that allows engineering, planning, and manufacturing to understand the actual execution of those plans. This paper addresses a methodology in place at the IBM Microelectronics facility that assists in analyzing the planned versus actual performance of the sampling and skipping plans. This is done by assessing the overall effects of the sampling and skipping plans, reporting the actual number of lots skipped and measured, and quantifying the time added to the process by oversampling lots. Data are collected directly from the actual lot and tool histories. All of these techniques combined allow for more effective planning and a reduction of the capacity needed for and utilized by the multiple product and technology types run in this fabricator

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

Date of Conference: