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TAT- and cost-reduction strategies in LSI manufacturing test process

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4 Author(s)
Fujioka, Hiromu ; Fac. of Eng., Osaka Univ., Japan ; Nakamae, Koji ; Chikamura, A. ; Kitamura, M.

Testing strategies in the test process composed of a wafer-probe testing phase, an LSI assembly and packaging phase, and a final testing phase are discussed to reduce the turn around time and costs with the manufacturing yield as a parameter through an event-driven simulation analysis. Three screening strategies considered in the wafer-probe testing phase are exhaustive testing, checkerboard sample testing and no wafer testing [NW]. The application of the simulation program to a test process for one-chip microcomputers showed that the NW strategy becomes effective in a yield range of larger than 70%. The simulation allows one to predict the effectiveness of the testing strategy with the manufacturing yield as a parameter

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI

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