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A smart CMOS imager with pixel level PWM signal processing

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5 Author(s)
Nagata, M. ; Fac. of Eng., Hiroshima Univ., Japan ; Homma, M. ; Takeda, N. ; Morie, T.
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A PWM signal CMOS imager which realizes block averaging and 2D projection of a thresholded image, in addition to row-parallel PWM readout with high-resolution gray scale, is reported. A pixel including a photo detector executes nondestructive conversion of integrated photo current to PWM signals or binary signals, which drives a readout bus in voltage or current mode. The average and 2D projection are realized with PWM signal addition techniques based on switched current integration and charge packet counting. An experimental imager including 56/spl times/56 pixels, an address signal generator, and a signal processing circuit are fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology. The PWM imager consumes only 2 /spl mu/W/pixel at a 3.3 V supply voltage for a readout operation.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999