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A new architecture which realizes the large bandwidth with virtually the same core circuitry as a conventional DRAM is proposed. The improved row block activation scheme combined with a categorized access sequence improves the bandwidth of the DRAM even with the shared sense amplifier scheme. The data efficiency of the random read/write mixed cycle is improved by the proposed delayed write operation, which fills the write to read command gap effectively. The proposed architecture is successfully examined in the 128 Mbit test vehicle fabricated with a 0.15 /spl mu/m CMOS process.