A robust 8F/sup 2/ ferroelectric RAM cell with depletion device (DeFeRAM)

This paper describes an area penalty free, leakage compensated and noise immune 8F/sup 2/ cell design suitable for high density low power FeRAM generations. The array concept features a 1TIC ferroelectric memory cell containing an additional depletion device (DeFeRAM) controlled by the passing word line in a folded bit line architecture. A highly reliable three level word line driver circuit design is discussed.