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An 8 b 500 MS/s full Nyquist cascade A/D converter

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5 Author(s)
Irie, K. ; Yokogawa Electr. Corp., Tokyo, Japan ; Kusayanagi, N. ; Kawachi, T. ; Nishibu, T.
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An 8 b 500 MS/s one-bit-per-stage cascade A/D converter (ADC) has been developed. We achieved 500 MHz one-clock conversion of all the cascade stages with a novel error suppression technique. The measured SNDR is 47 dB (7.6 effective bits) at a 100 kHz input, keeping more than 45 dB (7.2 effective bits) up to the Nyquist frequency. The power dissipation and the active area of the ADC core, including a 1.5 GHz bandwidth sample-and-hold amplifier, are 950 mW from a +2 V/-3.3 V supply and 5.5 mm/sup 2/, respectively.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999

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