Cart (Loading....) | Create Account
Close category search window

An 8 b 500 MS/s full Nyquist cascade A/D converter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Irie, K. ; Yokogawa Electr. Corp., Tokyo, Japan ; Kusayanagi, N. ; Kawachi, T. ; Nishibu, T.
more authors

An 8 b 500 MS/s one-bit-per-stage cascade A/D converter (ADC) has been developed. We achieved 500 MHz one-clock conversion of all the cascade stages with a novel error suppression technique. The measured SNDR is 47 dB (7.6 effective bits) at a 100 kHz input, keeping more than 45 dB (7.2 effective bits) up to the Nyquist frequency. The power dissipation and the active area of the ADC core, including a 1.5 GHz bandwidth sample-and-hold amplifier, are 950 mW from a +2 V/-3.3 V supply and 5.5 mm/sup 2/, respectively.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.