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Recent reports on high-speed CMOS D/A Converters (DACs) demonstrate clock rates and effective bandwidths of the well-known current-steering DAC architecture of 100's of MHz. In this work, new circuit design and layout methods are applied to a glitch-free 10 b DAC based on the pipelined charge redistribution architecture. Transients in the output current as codes change are called glitches, and because glitch characteristics depend nonlinearly on codes, they result in spurious tones in the output frequency spectrum. In the glitch-free DAC, on the other hand, the analog voltages are sampled and held at each clock cycle. The 0.6 /spl mu/m CMOS prototype described here clocks at up to 400 MS/s, and delivers a superior spurious-free dynamic range (SFDR) over the Nyquist band compared to other CMOS DACs. This circuit is part of a digitally based agile frequency synthesizer for a fast-frequency hopping wireless transmitter, and is intended to drive on-chip capacitor loads.