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10-100 Gb/s throughput CMOS techniques

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2 Author(s)
Svensson, C. ; Linkoping Univ., Sweden ; Edman, A.

Basic limitations to high data throughput chips in CMOS are described and methods for coping with these discussed. The proposed methods are demonstrated by two design examples;: a pipelined datapath architecture for high throughput protocol processing; and a shared buffer architecture for switching.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999

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