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A high-voltage output buffer fabricated on a 2 V CMOS technology

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1 Author(s)
Clark, L.T. ; Intel Corp., Chandler, AZ, USA

VLSI core voltages have scaled considerably below legacy I/O standards such as PCI which require tolerance of voltages between -1 V to over 6 V when power supply deviation and signal overshoot effects are considered. Circuit based dielectric protection has been demonstrated previously to address this problem for 3.3 V on a 2.5 V process. Gate oxide stress is dependent on the total stress time and magnitude of the stress over the life of the chip, which must be limited. Here, a 5 V PCI output buffer implemented on a standard 2 V process is presented which dynamically limits the DC stress to devices below 2.1 V and minimizes AC stress duration.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999