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This paper describes a low power, 1 Gbps, CMOS link with measured bit error rate (BER)<10/sup -14/. To obtain the low BER, skew between clock and data is detected and removed by using non-uniform tracked over-sampling technique with a high-resolution phase control. A delay-locked loop (DLL) with a wide operating frequency range of 250-750 MHz generates four phase sampling clocks.
Date of Conference: 17-19 June 1999