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An effective way to reduce the power consumption of a high-speed LSI is to use two supply voltages. Most circuit parts off the critical path can then operate at a supply voltage lower than that of parts in the critical path. Rows of logic-cell blocks for example, can be assigned to circuits for either a high or low supply voltage, and this approach has been used to reduce the power consumption of a 75-MHz 0.3-/spl mu/m bulk CMOS media processor using both 3.3-V and 1.9-V supply voltage. Here we use a fully depleted CMOS/SIMOX device and 2-V/1-V supply voltages to enhance the low-power characteristics of the two-supply-voltage technique with a little area penalty.