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840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to-processer communication

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5 Author(s)
Jae-Yoon Sim ; Dept. of Electr. Eng., Pohang Inst. of Sci. & Technol., South Korea ; Young-Soo Sohn ; Hong-June Park ; Chang-Hyun Kim
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An equalizing transceiver was designed for DRAM bus system and implemented using a 0.35 /spl mu/m CMOS technology. To maximize the data rate a one-to-eight demultiplexing scheme was used to remove inter-symbol interference. The maximum data rates were measured to be 840 Mb/s without loading and 760 Mb/s with the total capacitance load of 110 pF at the bit error rate less than 10/sup -12/. The chip size was 1500/spl times/700 /spl mu/m/sup 2/ and the power consumption was 150 mW at the supply voltage of 3.3 V.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999

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