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A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

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2 Author(s)
Xanthopoulos, T. ; MIT, Cambridge, MA, USA ; Chandrakasan, A.

This work describes the implementation of a DCT (Discrete Cosine Transform) chip targeted to low power video (MPEG2 MP@ML) and still image (JPEG) applications. The chip exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context (MSB rejection and row-column classification) along with standard voltage scaling techniques such as pipelining and parallelism.

Published in:

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Date of Conference:

17-19 June 1999