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Neural network controlled shift register traffic shaper for ATM networks

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4 Author(s)
Lakshminarayanan, G. ; Dept. of Electron. & Commun. Eng., Regional Eng. Coll., Tiruchirappalli, India ; George, B. ; Venkataramani, B. ; Ramakalyan, A.

In ATM networks several schemes have been proposed to shape the traffic in order to minimize the network congestion and increase channel throughput. A completely satisfactory solution has not yet been obtained due to conflicting requirements of accommodating complex variable bit rate traffic and supporting real time call admission and congestion control mechanism. The shift register traffic shaper (SRTS) scheme proposed by Radhakrishnan, Raghavan and Agrawala (see Comp. Net. & ISDN systems, Elsevier, vol. 28, p.453-69, 1996) performs better than LB mechanism by incorporating multiple windows accommodating different degrees of burstiness in the traffic. However the parameters of the SRTS scheme is insensitive to the congestion level at the ATM node. In this paper a two pronged approach is suggested and studied to combat congestion. The ANN monitors the congestion level at the ATM node and generates the control signals to the sources. The SRTS scheme modifies its parameters in response to this signal to keep the congestion under control. Depending upon the control signal received, the SRTS minimizes the congestion by either splitting the sources contending for network access into groups or by modifying the window parameters of individual SRTS. To validate these approaches an ANN is simulated and the optimum weight vector is obtained. An ATM node with traffic from sources with SRTS is simulated and the loss probability is obtained under different output burstiness. The results obtained confirms the effectiveness of staggering and modification of parameters of SRTS

Published in:

TENCON '98. 1998 IEEE Region 10 International Conference on Global Connectivity in Energy, Computer, Communication and Control  (Volume:1 )

Date of Conference:

1998