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Analysis of testable PLA designs

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2 Author(s)
X. -A. Zhu ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; M. A. Breuer

A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, and fully testable PLAs. The attributes that make a good testable design are then discussed. They fall into four categories: (1) testability characteristics; (2) effect on original design; (3) requirements of the application environment; and (4) design costs, i.e. how difficult it is to implement the technique.<>

Published in:

IEEE Design & Test of Computers  (Volume:5 ,  Issue: 4 )