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VLSI configurable delay commutator for a pipeline split radix FFT architecture

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3 Author(s)
Garcia, J. ; Fac. de Ciencias, Cantabria Univ., Santander, Spain ; Michell, J.A. ; Buron, A.M.

This paper presents a full custom one-bit slice delay commutator for a pipeline split radix FFT (SRFFT) architecture, implemented using the true single-phase-clock (TSPC) circuit technique and a 1.0-μm CMOS technology. This circuit can be configured or all intermediate SRFFT computation levels for transforms of lengths up to N=2048, where N is power of two. The circuit has been tested up to 200 MHz, having a power consumption of 1.1 W at 5 V of power supply

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Signal Processing, IEEE Transactions on  (Volume:47 ,  Issue: 11 )