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Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current

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3 Author(s)
J. G. Fossum ; Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA ; K. Kim ; Y. Chong

A simulation-based analysis of extremely scaled double-gate (DG) CMOS, emphasizing the effects of gate-induced drain leakage (GIDL) in DG MOSFETs, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in DG devices than in the single-gate counterparts. However, for asymmetrical (n+ and p+ polysilicon) gates, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p+ -gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits

Published in:

IEEE Transactions on Electron Devices  (Volume:46 ,  Issue: 11 )