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Design verification of the WE 32106 math accelerator unit

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1 Author(s)
Maurer, P.M. ; AT&T, Holmdel, NJ, USA

An overview is given of the MAU, an IEEE-compatible floating-point accelerator that operates as a coprocessor for the WE 32100 CPU. The chip provides virtually all the features that the IEEE-754 floating-point standard requires, with added software that provides a fully conforming system. A description is then given of the approach used for its design verification, which resulted in a unit that has exhibited no bugs, even two years after its first silicon implementation. Designers used two sets of tools during verification. With the first set, they reduced the time needed to create and execute tests and simplified the development of system tests. With the second set, they created a random test system, which plugged the holes left by system tests. Work underway to apply the techniques to other chips is described.

Published in:

Design & Test of Computers, IEEE  (Volume:5 ,  Issue: 3 )

Date of Publication:

June 1988

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