By Topic

Low-cost modular totally self-checking checker design for m-out-of-n code

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Wen-Feng Chang ; Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Cheng-Wen Wu

We present a low-cost (hardware-efficient) and fast totally self-checking (TSC) checker for m-out-of-n code, where m⩾3, 2m+1⩽n⩽4m. The checker is composed of four special adders which sum the 1s in the primary inputs added by appropriate constants, two ripple carry adders which sum the outputs of the biased-adders, and a t-variable two-rail code checker tree which compares the outputs of the two ripple carry adders, where k=[log2(n-m)+1]. All the modules are composed of 2-input gates and inverters. Compared with previous nonmodular methods, our TSC checker has a lower hardware and time complexity. Our method reduces the hardware complexity and circuit delay of the checker from O(n2) to O(n) and from O(n) to O(log2n), respectively. Compared with recent modular methods, our TSC checker has about the same hardware and time complexity, but is applicable to a much broader range of n. In summary, our method is superior to existing methods for the considered range of n. In addition, our TSC checker can easily be tested (the test set size of our TSC checker is relatively small) and implemented in VLSI for its modular structure

Published in:

IEEE Transactions on Computers  (Volume:48 ,  Issue: 8 )