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An on-chip multiprocessor architecture with a non-blocking synchronization mechanism

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5 Author(s)
Kobayashi, R. ; Dept. of Inf. Electron., Nagoya Univ., Japan ; Iwata, M. ; Ogawa, Y. ; Ando, H.
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The growth of perception that the superscalar approach is reaching its limits drives studies of on-chip multiprocessor (MP) architectures as the alternative. This paper proposes a new MP architecture, called SKY: which efficiently exploits thread-level parallelism using register-value communication and synchronization. The most distinctive feature of SKY from previously proposed MP architectures is its synchronization mechanism with non-blocking capability. It allows any subsequent instruction that is independent of instructions waiting for registers to be executed, enabling continuous out-of-order execution independently of inter-thread communication and synchronization. Our evaluation results in SPECint95 benchmark programs show that SKY with two processors achieves a speedup of up to 40% or an average of 12% over a much more complex single wide-issue superscalar processor with the nearly same amount of hardware

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EUROMICRO Conference, 1999. Proceedings. 25th  (Volume:1 )

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