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Self-testing of S-compatible test units in user-programmed FPGAs

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2 Author(s)
Tomaszewicz, P. ; Inst. of Telecommun., Warsaw Univ. of Technol., Poland ; Krasniewski, A.

A method for the development of a test plan for BIST based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone. Logic cones that satisfy single-generator compatibility requirement can be combinationally-exhaustively tested concurrently and are merged into a test block. The number of test blocks corresponds to the number of test sessions. For the presented algorithm of computing logic cones, a tool was developed. The presented experimental results are used to develop heuristic rules that control the logic cone merging process

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EUROMICRO Conference, 1999. Proceedings. 25th  (Volume:1 )

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