By Topic

Design of efficient SPARC cores for embedded systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Bautista, T. ; Univ. of Las Palmas, Spain ; Nunez, A.

The paper reports on design decisions taken in the modelling, design and implementation of a full set of SPARC v8 Integer Unit versions and gives data about the experimental results obtained. VHDL was the description language, Synopsys tools were for the logical synthesis, and Duet Technologies' Epoch was used for the physical layout of the final circuits. These have been carried out in a 0.35 μm, three-metal layer CMOS process. The description strategy and the design flow methodology allow us to obtain quantitative results that characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. This design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions

Published in:

EUROMICRO Conference, 1999. Proceedings. 25th  (Volume:1 )

Date of Conference: