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High-speed parallel Viterbi decoding: algorithm and VLSI-architecture

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2 Author(s)
Fettweis, G. ; IBM Almaden Res. Center, San Jose, CA, USA ; Meyr, H.

The Viterbi algorithm (VA) is considered as an example of a fairly complex algorithm that needs to be implemented for high-speed applications. A brief introduction to the algorithm is given, and the state of the art of high-speed Viterbi decoders is reviewed. The three principal levels of introducing additional parallelism into an algorithm-bit level, word level, and algorithm level-are outlined, and a solution for the VA at the bit level is indicated.<>

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Communications Magazine, IEEE  (Volume:29 ,  Issue: 5 )