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A new register allocation scheme for low-power data format converters

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3 Author(s)
Srivatsan, K. ; Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA ; Chakrabarti, C. ; Lucke, L.E.

In many applications, such as digital signal processing, data format converters (DFC) are used to reformat the data transferred between processing modules. Various methods have been proposed to synthesize DFC architectures while optimizing the number of registers used to store the data. In this brief, we present a new register allocation scheme which not only minimizes the number of registers, but also minimizes the power consumption in the DFC. Low-power DFC's are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over precious techniques

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:46 ,  Issue: 9 )