Cart (Loading....) | Create Account
Close category search window
 

Design of ADPLL for both large lock-in range and good tracking performance

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Nam-Guk Kim ; Dept. of Electr. Eng., Seoul Nat. Univ., South Korea ; In-Joong Ha

This paper describes a new all-digital phase locked loop (ADPLL). The proposed ADPLL contains a frequency offset estimator and a phase-error estimator. Thereby, it can provide both large lock-in range and good tracking performance. Furthermore, it does not suffer severely from the phase jitter due to the quantization effect of the numerically controlled oscillator. In addition to some mathematical performance analysis, various simulation and experimental results are also presented to illuminate further the practical use and the excellent performance of the proposed ADPLL

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:46 ,  Issue: 9 )

Date of Publication:

Sep 1999

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.