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Ladder derived switched-current decimators and interpolators

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2 Author(s)
Ng, A.E.J. ; Dept. of Electron. & Electr. Eng., Glasgow Univ., UK ; Sewell, J.I.

Switched-current elliptic decimators and interpolators based on bilinear-transformed low-sensitivity ladder structures are proposed. The combination of polyphase networks and doubly terminated ladder structures preserve low passband sensitivity and maximizes time for settling by operating at the lower sampling frequency. The decimators are derived via a z-domain multirate transformation procedure. Two different types of decimator architectures, finite-impulse response (FIR)-infinite-impulse response (IIR) cascade (FIC) and multiple feed-in (MFI) are presented and compared. The complementary IIR-FIR cascade (IFC) and multiple feed-out (MFO) interpolator structures are obtained by direct transposition, which avoids the need for redesign. A third-order elliptic low pass filter is used as prototype for deriving the decimators and interpolators. The circuits are verified by SCNAP4 and HSPICE simulations

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:46 ,  Issue: 9 )