By Topic

Dynamic algorithm transforms for low-power reconfigurable adaptive equalizers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Goel, M. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Shanbhag, N.R.

In this paper, we present low-power reconfigurable adaptive equalizers derived via dynamic algorithm transforms (DATs). The principle behind DAT is that conventional signal processing systems are designed for the worst case and are not energy-optimum on average. Therefore, significant energy savings can be achieved by optimally reconfiguring the hardware in these situations. Practical reconfiguration strategies for adaptive filters are presented. These strategies are derived as a solution to an optimization problem. The optimization problem has energy as the objective function and a constraint on the algorithm performance (specifically the SNR). The DAT-based adaptive filter is employed as an equalizer for a 51.84 Mb/s very high speed digital subscriber loop (VDSL) over 24-pair BKMA cable. The channel nonstationarities are due to variations in cable length and number of far end crosstalk (FEXT) interferers. For this application, the traditional design is based on 1 kft cable length and 11 FEXT interferers. It was found that up to 81% energy savings can be achieved when cable length varies from 1-0.1 kft and the number of FEXT interferers varies from 11 to 4. On the average, 53% energy savings are achieved as compared with the conventional worst-case design

Published in:

Signal Processing, IEEE Transactions on  (Volume:47 ,  Issue: 10 )