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Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic

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2 Author(s)
L. -C. E. Liu ; Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA ; C. Sechen

We present a chip-level global router based on a new, more accurate global routing model for the multilayer macro-cell (building block) technology. The routing model uses a three-dimensional mixed directed/undirected routing graph, which provides not only the topological information but also the layer information. The irregular routing graph closely models the multilayer routing problem, so the global router can give an accurate estimate of the routing resources needed. Route-searching is formulated as the Steiner problem in networks (graph Steiner tree problem). Although the Steiner problem in networks is an NP-hard problem, it can generate better routes than other approaches. Previously published Steiner tree heuristics can not handle the complexity of the modern routing graphs. We developed an improved Steiner tree heuristic algorithm which can take advantage of the features of routing graphs. Tested on industrial circuits, our algorithm yields comparable results while having dramatically lower time and space complexities than the leading heuristics. The efficiency and effectiveness of our algorithm make our global router applicable to large industrial circuits, easily handling multilayer problems consisting of 200 macro cells and 10000 nets. While minimizing the wire length, our global router can also minimize the number of vias or solve the routing resource congestion problems.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:18 ,  Issue: 10 )