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Hardware/software co-synthesis with memory hierarchies

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2 Author(s)
Yanbing Li ; Synopsys Inc., Mountain View, CA, USA ; Wolf, W.H.

This paper introduces the first hardware/software co-synthesis algorithm of distributed real-time systems that optimizes the memory hierarchy along with the rest of the architecture. Memory hierarchies (caches) are essential for modern embedded cores to obtain high performance. They also represents a significant portion of the cost, size and power consumption of many embedded systems. Our algorithm synthesizes a set of real-time tasks with data dependencies onto a heterogeneous multiprocessor architecture that meets the performance constraints with minimized cost. Unlike previous work in co-synthesis, our algorithm not only synthesizes the hardware and software portions of the applications, but also the memory hierarchies. It chooses cache sizes and allocates tasks to caches as part of cosynthesis. The algorithm is built upon a task-level performance model for memory hierarchies. Experimental results, including examples from the literature and results on real-life examples such as an MPEG-2 encoder, show that our algorithm is efficient, and compared with existing algorithms, it can reduce the overall cost of the synthesized system

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:18 ,  Issue: 10 )