By Topic

Architecture for fault diagnosis of CMOS ICs with BIC based IDDQ testing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Segura, J. ; Dept. of Phys., Balearic Islands Univ., Palma de Mallorca ; Isern, E. ; Roca, M.

An architecture for simplifying fault diagnosis is presented. The method is applied to circuits incorporating built-in current (BIC) sensors and is based on hardware partitioning, does not increase the number of pins and is independent of the fault diagnosis heuristic at the logic level

Published in:

Electronics Letters  (Volume:35 ,  Issue: 14 )