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AER image filtering architecture for vision-processing systems

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3 Author(s)
Serrano-Gotarredona, T. ; Inst. de Microelectron., CNM, Seville, Spain ; Andreou, A.G. ; Linares-Barranco, B.

A VLSI architecture is proposed for the realization of real-time two-dimensional (2-D) image filtering in an address-event-representation (AER) vision system. The architecture is capable of implementing any convolutional kernel F(x,y) as long as it is decomposable into x-axis and y-axis components, i.e., F(x,y)=H(x)V(y), for some rotated coordinate system {x,y} and if this product can be approximated safely by a signed minimum operation. The proposed architecture is intended to be used in a complete vision system, known as the boundary contour system and feature contour system (BCS-FCS) vision model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and some electrical simulations

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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:46 ,  Issue: 9 )