By Topic

High-efficiency harmonic loaded oscillator with low bias using a nonlinear design approach

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Moon-Que Lee ; Dept. of Satellite Commun. Syst., Electron. & Telecommun. Res. Inst., Taejon, South Korea ; Seung-June Yi ; Sangwook Nam ; Youngwoo Kwon
more authors

We present a design method for an optimized high-efficiency harmonic loaded oscillator. The proposed approach predicts the performance of oscillators including output power, dc-RF conversion efficiency, and dc-bias current shift during start-up transition. In this method, the performance of the oscillator can he optimized based on the performance analysis of the active device under the assumed operation conditions. The effects of fundamental and harmonic loading on output power and efficiency are investigated by the proposed approach. Two kinds of stability conditions are addressed for an oscillator initially biased at a low gate voltage. Using the proposed approach, we design an oscillator that has a high efficiency of 61% at 1.86 GHz with a very low bias voltage of 2.0 V

Published in:

Microwave Theory and Techniques, IEEE Transactions on  (Volume:47 ,  Issue: 9 )