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Interconnect performance modeling for 3D integrated circuits with multiple Si layers

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2 Author(s)
Souri, S.J. ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; Saraswat, K.C.

Long interconnect RC delay is increasing rapidly with chip size, limiting chip performance. 3D device integration in multiple layers of Si promises to increase transistor packing density and reduce RC time delay through reducing chip size. This paper offers a quantitative approach to compare current technology chip performance to that of 3D ICs

Published in:

Interconnect Technology, 1999. IEEE International Conference

Date of Conference:

1999