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Hierarchical analogue design and behavioural modelling

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7 Author(s)
Zimmer, T. ; Lab. IXL, Bordeaux I Univ., Talence, France ; Milet-Lewis, N. ; Fakhfakh, A. ; Ardouin, B.
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This paper describes a new project oriented course which has been set-up recently at the University of Bordeaux, France, in co-operation with the institute of Microelectronics Bordeaux IXL. This course, held within the curriculum of the microelectronics engineer education, introduces the concept of hierarchical design of analogue circuits and analogue HDL like VerilogA or VHDL-AMS circuit modelling to the students. It is composed of a short lecture part and a major laboratory part where well-known design software is used. A phase-locked-loop (PLL), defined in the literature, has been taken as a design example to be investigated by the students. The scope of this course is to familiarise the behavioural modelling approach during the design phase of analogue circuits

Published in:

Microelectronic Systems Education, 1999. MSE'99. IEEE International Conference on

Date of Conference:

1999

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