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Training IP creators and integrators

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5 Author(s)
Bouldin, D. ; Dept. of Electr. Eng., Tennessee Univ., Knoxville, TN, USA ; Natarajan, S. ; Levine, B. ; Tan, C.
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Intellectual property (IP) blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time to market which results in increased profits. Alliances of companies have been formed to support an open market for IP and standards are being devised to ensure the quality of this IP. Also, a web-based network has been set up to facilitate the matching of providers and consumers. However, a significant problem still needs be addressed: namely, the widespread training of IP creators and integrators. Universities have been offering courses which involve logic synthesis and simulation using VHDL or Verilog along with verification using FPGAs. Now that standards for IP reuse are being developed, these courses need to require students to develop and integrate IP blocks which are compliant with the desired quality level. In this paper, we describe the procedure that we have begun using at the University of Tennessee to train IP creators and integrators to meet these new challenges. In addition, we propose the widespread adoption of this type of training and the development of an infrastructure to support the dissemination of IP shareware

Published in:

Microelectronic Systems Education, 1999. MSE'99. IEEE International Conference on

Date of Conference:

1999