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An arbitrarily fast block processing architecture for decision feedback equalizers

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2 Author(s)
Meng-Lin Yu ; Lucent Technol., AT&T Bell Labs., Holmdel, NJ, USA ; Azadet, K.

In this paper, a novel architecture is proposed to solve the decision feedback equalizer (DFE) critical path problem by parallel processing. This architecture uses the block processing technique. A block processing DFE with block factor of N takes N inputs and produces N outputs in parallel. Since each output computation depends on previous decisions, the computation of the N outputs forms a dependency chain in block processing DFEs and requires N-1 multiplexing delay time when it is done sequentially. Our architecture employs a fast, O(logN) multiplexing delay algorithm to resolve the output dependency and thus speeds up parallel block processing DFEs. Further, our architecture can be used with pipelining to completely eliminate the critical path problem. This architecture enables digital DFEs to be used in many important applications, such as very high speed data communication systems

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VLSI Technology, Systems, and Applications, 1999. International Symposium on

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